 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| E2G1053-18-54 Semiconductor MSM56V16800E Semiconductor This version: Jul. 1998 MSM56V16800E 2-Bank 1,048,576-Word 8-Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MSM56V16800E is a 2-bank 1,048,576-word 8-bit synchronous dynamic RAM, fabricated in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs and outputs are LVTTL compatible. FEATURES Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell 2-bank 1,048,576-word 8-bit configuration 3.3 V power supply, 0.3 V tolerance Input : LVTTL compatible Output : LVTTL compatible Refresh : 4096 cycles/64 ms Programmable data transfer mode - CAS latency (1, 2, 3) - Burst length (1, 2, 4, 8, full page) - Data scramble (sequential, interleave) * CBR auto-refresh, Self-refresh capability * Package: 44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM56V16800E-xxTS-K) xx indicates speed rank. * * * * * * * PRODUCT FAMILY Family MSM56V16800E-8 MSM56V16800E-10 Max. Frequency 125 MHz 100 MHz Access Time (Max.) tAC1 22 ns 27 ns tAC2 10 ns 9 ns tAC3 6 ns 9 ns 1/30 Semiconductor PIN CONFIGURATION (TOP VIEW) MSM56V16800E VCC DQ1 VSSQ DQ2 VCCQ DQ3 VSSQ DQ4 VCCQ NC NC WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 DQM DQi VCC VSS VCCQ VSSQ NC 44 VSS 43 DQ8 42 VSSQ 41 DQ7 40 VCCQ 39 DQ6 38 VSSQ 37 DQ5 36 VCCQ 35 NC 34 NC 33 DQM 32 CLK 31 CKE 30 NC 29 A9 28 A8 27 A7 26 A6 25 A5 24 A4 23 VSS 44-Pin Plastic TSOP (II) (K Type) Pin Name CLK CS CKE A0 - A10 A11 RAS CAS WE Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Pin Name Function Data Input/Output Mask Data Input/Output Power Supply (3.3 V) Ground (0 V) Data Output Power Supply (3.3 V) Data Output Ground (0 V) No Connection Note: The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/30 Semiconductor MSM56V16800E PIN DESCRIPTION CLK CS CKE Fetches all inputs at the "H" edge. Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE and DQM. Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address: RA0 - RA10 Column address: CA0 - CA8 A11 RAS CAS WE DQM DQi Masks the read data of two clocks later when DQM is set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when DQM is set "H" at the "H" edge of the clock signal. Data inputs/outputs are multiplexed on the same pin. Functionality depends on the combination. For details, see the function truth table. Selects bank to be activated during row address latch time and selects bank for precharge and read/ write during column address latch time. A11 = "L" : Bank A, A11 = "H" : Bank B 3/30 Semiconductor BLOCK DIAGRAM MSM56V16800E CKE CLK CS RAS CAS WE DQM Timing Register Programming Register Latency & Burst Controller I/O Controller Bank Controller A11 A0 A11 Internal Col. Address Counter Input Data Register 9 Input Buffers 8 8 9 Column Address Buffers Column Decoders Sense Amplifier Internal Row Address Counter 8 Read Data Register 8 8 Output Buffers DQ1 DQ8 Row Decoders Word Drivers 8Mb Memory Cells 8Mb Memory Cells 12 Row Address Buffers 12 Row Decoders Word Drivers Sense Amplifier Column Decoders 4/30 Semiconductor MSM56V16800E ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (Voltages referenced to VSS) Parameter Voltage on Any Pin Relative to VSS VCC Supply Voltage Storage Temperature Power Dissipation Short Circuit Current Operating Temperature Symbol VIN, VOUT VCC, VCCQ Tstg PD* IOS Topr Rating -0.5 to VCC + 0.5 -0.5 to 4.5 -55 to 125 600 50 0 to 70 Unit V V C mW mA C *: Ta = 25C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC, VCCQ VIH VIL Min. 3.0 2.0 VSS - 2.0 Typ. 3.3 -- -- (Voltages referenced to VSS = 0 V) Max. 3.6 VCC + 2.0 0.8 Unit V V V Capacitance (VCC = 1.4 V, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (CLK) Input Capacitance (CKE, CS, RAS, CAS, WE, DQM, A0 - A11) Input/Output Capacitance (DQ1 - DQ8) Symbol CCLK CIN CI/O Min. 2.5 2.5 4 Max. 4 5 6.5 Unit pF pF pF 5/30 Semiconductor DC Characteristics Condition Parameter Symbol Bank -- -- -- -- One Bank Active CKE -- -- -- -- Others IOH = -2 mA IOL = 2 mA -- -- MSM56V16800E Output High Voltage VOH Output Low Voltage Input Leakage Current Output Leakage Current VOL ILI ILO ICC1 Average Power Supply Current (Operating) Version Unit Note E-8 E-10 Min. Max. Min. Max. 2.4 -- -- 2.4 V -- -10 -10 -- 0.4 10 10 85 -- -10 -10 -- 0.4 10 10 70 V mA mA mA 1, 2 CKE VIH tCC = min tRC = min No Burst CKE VIH tCC = min tRC = min tRRD = min No Burst CKE VIH tCC = min CKE VIL tCC = min ICC1D Both Banks Active -- 115 -- 100 mA 1, 2 Power Supply Current (Stand by) ICC2 Both Banks Precharge -- 40 -- 30 mA 3 Average Power ICC3S Both Banks Active Supply Current (Clock Suspension) Average Power Supply Current (Active Stand by) Power Supply Current (Burst) Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power down) ICC3 One Bank Active Both Banks Active One Bank Active Both Banks Precharge Both Banks Precharge -- CKE VIH tCC = min -- CKE VIH tCC = min CKE VIH tCC = min tRC = min CKE VIL tCC = min -- CKE VIL tCC = min -- 3 -- 3 mA 2 45 -- 35 mA 3 ICC4 ICC5 -- 105 -- 90 mA 1, 2 -- 80 -- 70 mA 2 ICC6 2 -- 2 mA ICC7 2 -- 2 mA Notes: 1. Measured with outputs open. 2. The address and data can be changed once or left unchanged during one cycle. 3. The address and data can be changed once or left unchanged during two cycles. 6/30 Semiconductor MSM56V16800E Mode Set Address Keys CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CL Reserved 1 2 3 Reserved Reserved Reserved Reserved 0 1 Burst Type A3 BT Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 BT = 1 1 2 4 8 Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved Note: A7, A8, A9, A10 and A11 should stay "L" during mode set cycle. POWER ON SEQUENCE 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 ms or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply a CBR auto-refresh eight or more times. 5. Enter the mode register setting command. 7/30 Semiconductor AC Characteristics Parameter CL = 3 Clock Cycles Time CL = 2 CL = 1 CL = 3 Access Time from CL = 2 Clock CL = 1 Clock "H" Pulse Time Clock "L" Pulse Time Input Setup Time Input Hold Time Output Low Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock RAS Cycle Time RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time tAC tCH tCL tSI tHI tOLZ tOHZ tOH tRC tRP tRAS tRCD tWR tCC Symbol MSM56V16800E-8 Min. 8 12 24 -- -- -- 3 3 2 1 3 -- 3 70 20 48 20 8 20 20 -- 10 -- 1 1 2 0 0 CL 3 Max. -- -- -- 6 10 22 -- -- -- -- -- 9 -- -- -- 105 -- -- -- -- 64 -- 3 MSM56V16800E Note 1, 2 MSM56V16800E-10 Min. 10 15 30 -- -- -- 3 3 3 1 3 -- 3 90 30 60 30 15 20 20 -- 10 -- 1 1 2 0 0 CL 3 Max. -- -- -- 9 9 27 -- -- -- -- -- 8 -- -- -- 105 -- -- -- -- 64 -- 3 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns Cycle Cycle Cycle Cycle Cycle Cycle Cycle 3 3, 4 3, 4 3, 4 Write Command Input Time tOWD from Output RAS to RAS Bank Active Delay Time Refresh Time Power-down Exit Set-up Time Input Level Transition Time CAS to CAS Delay Time (Min.) Clock Disable Time from CKE Data Output High Impedance Time from DQM Data Input Mask Time from DQM Data Input Time from Write Command Data Output High Impedance Time from Precharge Command tRRD tREF tPDE tT lCCD lCKE lDOZ lDOD lDWD lROH lMRD Active Command Input Time from Mode Register Set Command Input (Min.) 8/30 Semiconductor Notes : 1. AC measurements assume that tT = 1 ns. 2. The reference level for timing of input signals is 1.4 V. 3. Output load. Output MSM56V16800E 50 pF External Load 4. The access time is defined at 1.5 V. 5. If tT is longer than 1 ns, then the reference level for timing of input signals is VIH and VIL. 9/30 Semiconductor TIMING WAVEFORM Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE DQM , , , , , MSM56V16800E 16 17 18 19 tRC tRP tRCD Ra Ca0 Rb Cb0 Ra Rb tOH Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 tAC tOHZ tWR Row Active Read Command Row Active Write Command Precharge Command Precharge Command 10/30 Semiconductor MSM56V16800E Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 2, Burst Length = 4 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ,,, ,, CLK tCC tCL CKE CS High tHI tSI RAS CAS tSI tHI lCCD tSI tSI tSI ADDR Ra Ca Cb Cc tHI tHI A11 BS BS BS BS BS A10 DQ Ra tAC tHI Qa Db Qc tOLZ tSI tOH tOHZ tOWD tHI WE tSI DQM Row Active Write Command Precharge Command Read Command Read Command 11/30 Semiconductor *Notes: MSM56V16800E 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE and DQM are invalid. 2. When issuing an active, read or write command, the bank is selected by A11. A11 0 1 Active, read or write Bank A Bank B 3. The auto precharge function is enabled or disabled by the A10 input when the read or write command is issued. A10 0 1 0 1 A11 0 0 1 1 Operation After the end of burst, bank A holds the idle status. After the end of burst, bank A is precharged automatically. After the end of burst, bank B holds the idle status. After the end of burst, bank B is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A10 and A11 inputs. A10 0 0 1 A11 0 1 X Operation Bank A is precharged. Bank B is precharged. Both banks A and B are precharged. 5. The input data and the write command are latched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1 CLK + tOHZ) after DQM entry. 12/30 Semiconductor Page Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE DQM *Notes: ,, , , , , , , , ,, 17 18 19 MSM56V16800E High Bank A Active lCCD Ca0 Cb0 Cc0 Cd0 Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 tOWD tWR *Note2 *Note1 Read Command Read Command Write Command Write Command Precharge Command 1. To write data before a burst read ends, DQM should be asserted three cycles prior to the write command to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. 13/30 ,,,, , ,, ,, , ,, Semiconductor MSM56V16800E Read & Write Cycle with Auto Precharge @ Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS High RAS CAS tRRD ADDR Ra Rb Ca Cb A11 A10 WE Ra Rb CAS Latency = 1 DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 A-Bank Precharge Start DQM CAS Latency = 2 DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 A-Bank Precharge Start DQM CAS Latency = 3 DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 A-Bank Precharge Start tWR DQM Row Active (A-Bank) A Bank Read with Auto Precharge Row Active (B-Bank) B Bank Write with Auto Precharge B Bank Precharge Start Point 14/30 Semiconductor Bank Interleave Random Row Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE DQM ,,, ,, , MSM56V16800E 18 19 High tRC tRRD RAa CAa RBb CBb RAc CAc RAa RBb RAc QAa0 QAa1 QAa2 QAa3 QBb1 QBb2 QBb3 QBb4 QAc0 QAc1 QAc2 QAc3 Row Active (A-Bank) Read Command (A-Bank) Read Command (B-Bank) Read Command (A-Bank) Row Active (B-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) Row Active (A-Bank) 15/30 Semiconductor MSM56V16800E , ,,, , , , ,, , Bank Interleave Random Row Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS High RAS CAS ADDR RAa CAa RBb CBb RAc CA A11 A10 DQ RAa RBb RAc DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 WE DQM Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Precharge Command (A-Bank) Write Command (B-Bank) Write Command (A-Bank) Row Active (A-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) 16/30 Semiconductor Bank Interleave Page Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE DQM *Note: , ,,, MSM56V16800E 16 17 18 19 High *Note1 RAa CAa RBb CBb CAc CBd CAe RAa RAa QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 lROH Row Active (A-Bank) Row Active (B-Bank) Read Command (B-Bank) Precharge Command (A-Bank) Read Command (A-Bank) Read Command (B-Bank) Read Command (A-Bank) Read Command (A-Bank) 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 17/30 Semiconductor Bank Interleave Page Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MSM56V16800E 17 18 19 CLK High CKE CS ,, , RAS CAS ADDR RAa CAa RBb CBb CAc CBd A11 A10 DQ RAa RAb DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 WE DQM Row Active (A-Bank) Row Active (B-Bank) Write Command (B-Bank) Write Command (A-Bank) Write Command (B-Bank) Write Command (A-Bank) Precharge Command (Both Bank) 18/30 Semiconductor MSM56V16800E Bank Interleave Random Row Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE DQM ,,,, , , ,, High RAa CAa RBb CBb RAc CAc RAa RBb RAc QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 QAc3 Row Active (A-Bank) Row Active (B-Bank) Write Command (B-Bank) Read Command (A-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Row Active (A-Bank) 19/30 Semiconductor MSM56V16800E Bank Interleave Page Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE DQM , ,,,, ,, , High CAa0 CBb0 CAc0 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 QAc3 Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) 20/30 Semiconductor MSM56V16800E Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 *Note1 *Note1 CKE CS RAS CAS ADDR Ra Ca Cb Cc A11 A10 DQ1 - 8 WE Ra Qa0 Qa1 Qa2 Qb0 Qb1 Dc0 Dc2 *Note2 tOHZ tOHZ *Note3 DQM Row Active Read Command CLOCK Suspension Read Command CLK *Notes: , , ,, Read DQM Read DQM Write Command Write DQM CLOCK Suspension Write DQM 1. When Clock Suspension is asserted, the next clock cycle is ignored. 2. When DQM is asserted, the read data after two clock cycles is masked. 3. When DQM is asserted, the write data in the same clock cycle is masked. 21/30 Semiconductor Read to Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE DQM *Note: ,, , , ,, MSM56V16800E 16 17 18 19 *Note1 tRCD Ra Ca0 Ca0 Ra Da0 Da1 Da2 Da3 tWR Row Active Read Command Precharge Command Write Command 1. In case CAS latency is 3, READ can be interrupted by WRITE. The minimum command interval is [burst length + 1] cycles. DQM must be high at least 3 clocks prior to the write command. 22/30 Semiconductor Read Interruption by Precharge Command @ Burst Length = 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 MSM56V16800E , , ,,, , ,, ,,, , , ,, 14 15 16 17 18 19 CLK CKE CS High RAS CAS ADDR Ra Ca A11 A10 WE Ra CAS Latency = 1 DQ *Note1 lROH Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 DQM CAS Latency = 2 DQ *Note2 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 lROH DQM CAS Latency = 3 DQ *Note3 Qa5 Qa0 Qa1 Qa2 Qa3 Qa4 lROH DQM Row Active Read Command Precharge Command *Notes: 1. When the CAS latency = 1, and if row precharge is asserted before a burst read ends, then the read data will not output after the next clock cycle of the precharge command. 2. When the CAS latency = 2, and if row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. 3. When the CAS latency = 3, and if row precharge is asserted before burst read ends, then the read data will not output after the third clock cycle of the precharge command. 23/30 , , , , , ,, Semiconductor MSM56V16800E Power Down Mode @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tSI *Note1 tPDE *Note2 tSI CKE CS tSI RAS CAS ADDR Ra Ca A11 A10 DQ Ra Qa0 Qa1 Qa2 WE DQM Row Active Power-down Entry Power-down Exit Clock Suspention Entry Clock Suspention Exit Read Command Precharge Command *Notes: 1. When both banks are in precharge state, and if CKE is set low, then the MSM56V16800E enters powerdown mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, CKE has to be set high for longer than tPDE (1 CLK). 24/30 Semiconductor Self Refresh Cycle 0 1 2 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE DQM , ,,, , MSM56V16800E tRC tSI Ra BS Ra Hi - Z Hi - Z Self Refresh Entry Self Refresh Exit Row Active 25/30 Semiconductor Mode Register Set Cycle 0 1 2 3 4 MSM56V16800E Auto Refresh Cycle 0 1 2 3 4 CLK CKE CS RAS CAS ADDR DQ WE DQM , , , , ,,, , 5 6 5 6 7 8 9 10 11 12 High High lMRD tRC key Ra Hi - Z Hi - Z MRS New Command Auto Refresh Auto Refresh 26/30 Semiconductor MSM56V16800E FUNCTION TRUTH TABLE (Table 1) (1/2) Current State1 CS RAS CAS WE BA Idle H L L L L L L L Row Active H L L L L L L Read H L L L L L L L Write H L L L L L L L Read with Auto Precharge H L L L L L L Write with Auto Precharge H L L L L L L X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H H H L L X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H L X H H L L H L X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L X X X H L H L X X X X BA BA BA BA X L X X BA BA BA BA X X X BA BA BA BA BA X X X BA BA BA BA BA X X X BA BA X BA X X X BA BA X BA X ADDR X X X CA RA A10 X OP Code X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 X RA, A10 X X X X CA, A10 X RA, A10 X NOP NOP ILLEGAL 2 ILLEGAL 2 Row Active NOP 4 Auto-Refresh or Self-Refresh 5 Mode Register Write NOP NOP Read Write ILLEGAL 2 Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Reserved Term Burst, start new Burst Read Term Burst, start new Burst Write ILLEGAL 2 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) ILLEGAL 2 Term Burst, start new Burst Read Term Burst, start new Burst Write ILLEGAL 2 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL Action 27/30 Semiconductor MSM56V16800E FUNCTION TRUTH TABLE (Table 1) (2/2) Current State1 CS RAS CAS WE BA Precharge H L L L L L L Write Recovery H L L L L L L Row Active H L L L L L L Refresh H L L L L Mode Register Access H L L L L ABBREVIATIONS RA = Row Address CA = Column Address Notes: X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X X X X X X X X ADDR X X X CA RA A10 X X X X CA RA A10 X X X X CA RA A10 X X X X X X X X X X X NOP --> Idle after tRP NOP --> Idle after tRP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 NOP 4 ILLEGAL NOP NOP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Row Active after tRCD NOP --> Row Active after tRCD ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Idle after tRC NOP --> Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL Action BA = Bank Address AP = Auto Precharge NOP = No OPeration command 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of lCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. 28/30 Semiconductor MSM56V16800E FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) CKEn-1 Self Refresh H L L L L L L Power Down H L L L L L L All Banks Idle (ABI) 6 CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L CS RAS CAS WE X H L L L L X X H L L L L X X H L L L L L L X X X X X X X H H H L X X X H H H L X X X H H H L L L X X X X X X X H H L X X X X H H L X X X X H H L H L L X X X X X X X H L X X X X X H L X X X X X H L X L H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X X X X X X X X X INVALID Action Exit Self Refresh --> ABI Exit Self Refresh --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ILLEGAL ILLEGAL ILLEGAL 6 NOP (Continue power down mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension H H H H H H H H L Any State Other than Listed Above H H L L Note: 6. Power-down and self refresh can be entered only when all the banks are in an idle state. 29/30 Semiconductor MSM56V16800E PACKAGE DIMENSIONS (Unit : mm) TSOPII44-P-400-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.54 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 30/30 |
Price & Availability of MSM56V16800E
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |